1. Field of the Invention
The present invention relates to a system memory to be used in a digital processor such as a computer, and it also relates to a microcomputer comprising the same.
2. Description of the Related Art
FIG. 7 exemplarily shows a conventional system memory provided with a read only memory (ROM) and a random access memory (RAM). This system memory comprises four memory devices 14a, 14b, 14c, and 14d, a central processing unit (CPU) 11, and a memory controller 12.
Between the CPU 11 and the memory controller 12, address signals 210, data signals 220, and control signals 230 are transmitted in the directions of the arrows as shown in FIG. 7. Moreover, between the memory controller 12 and the memory devices 14a to 14d, address signals 211, data signals 221, chip enable (CE) signals 232 to 235, a write enable (WE) signal 236, and an output enable (OE) signal 237 are transmitted in the directions shown by the arrows in FIG. 7.
FIG. 9 schematically shows the memory space of the conventional system memory comprising the memory devices 14a to 14d. A memory space having a capacity of 1 megabyte (MB) is divided into four areas a to d each having a capacity of 256 kilobytes (kB). The four memory devices 14a to 14d are allocated to the four areas a to d, respectively. More specifically, the memory devices 14a and 14c functioning as ROMs are allocated to the areas a and c, and the memory devices 14b and 14d functioning as RAMs are allocated to the areas b and d. However, each of the areas a to d can arbitrarily be allocated for the ROMs or RAMs. Herein, the conventional memory devices 14a to 14d are each made of a single memory chip.
FIG. 8 shows a conventional architecture of the memory controller 12. The CE signals 232 to 235 are generated from a memory read signal /MR and a memory write signal /MW of the control signals 230, and address signals A18 and A19. The address signals A18 and A19 corresponding to the most and second most significant of the address signals (A0 to A19) generated from the address signals 210. The address signals each have a capacity of 1 bit and designate a location in the memory space. One of the four CE signals 232 to 235 is activated so as to select one memory device corresponding to the activated CE signals among the four memory devices 14a to 14d.
In the memory controller 12, the WE signal 236 and the OE signal 237 are generated from the memory write signal /MW and the memory read signal /MR, respectively. The address signals 211 are generated from address latch enable signals ALE and the address signals 210. The data signals 221 are transmitted from the CPU 11 to the memory devices 14a to 14d, and vice versa, via the memory controller 12 in accordance with a signal /R indicating a transmitting direction of the data.
However, according to the above conventional system memory, the maximum size of the area allocated for the memory device (ROM or RAM) is limited depending upon the capacity of the memory device (memory chip). Therefore, in the case where the memory space is allocated for ROMs and RAMs, a decrease in the number of memory devices to be used results in the limitation of the allocation. That is, the degree of freedom for the allocation is remarkably narrowed, thereby making it difficult to design the system memory.
On the other hand, in the case where a number of memory devices (ROMs and RAMs) are used for the memory space, each capacity of the memory devices (for example, 256 kB) cannot be utilized sufficiently and effectively. Furthermore, the address decode circuit becomes much more complicated due to the necessity of selecting a desired memory device among a number of memory devices.
That is, for the production of a system memory with a memory space having a capacity of 1 MB, composed of ROMs and RAMs each having a capacity of 256 bytes, 4096 memory devices are required. However, when so many memory devices are used in the system memory, wirings connected around the memory devices become complicated, and thus the system memory becomes complicated and inefficient. Furthermore, there is no existing memory device having such a small capacity (256 B) in actuality.
Therefore, conventionally, there has only been a system memory with a memory space comprising a relatively small number of ROMs and RAMs each having a capacity of several kB or more as shown in FIG. 9.
As is apparent from the above, according to the prior art, it is impossible to realize a system memory with a memory space in which a number of write and read areas and read only areas are mixedly included, and an address can freely be allocated as desired. That is, neither memory space having a capacity of 1 MB composed of ROMs and RAMs each having a small capacity (256 B), nor memory space in which such ROMs and RAMs are included in a freely mixed manner can be realized conventionally.